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| PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUITS PD70F3102-33 V850E/MS1 32-/16-BIT SINGLE-CHIP MICROCONTROLLER TM The PD70F3102-33 is a product that substitutes the internal mask ROM of the PD703102-33 with flash memory. This enables users to perform on-board program writing and erasure, enabling effective evaluation during system development, small-lot production of multiple devices, and rapid production start, and quick development and time-to-market. A version using a 3.3 V power supply for external pins, the PD70F3102-A33, is also available. For additional information, refer to the following user's manuals. Be sure to read them before starting design. V850E/MS1 User's Manual Hardware: U12688E V850E/MS1 User's Manual Architecture: U12197E FEATURES * PD703102-33 compatible Can be replaced by the PD703102-33 with internal mask ROM for mass production * Internal flash memory: 128 KB ORDERING INFORMATION Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) PD70F3102GJ-33-8EU PD70F3102GJ-33-UEN The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13844EJ2V0DS00 (2nd edition) Date Published July 2000 N CP(K) Printed in Japan The mark shows major revised points. (c) 1999 PD70F3102-33 PIN CONFIGURATION (Top View) 144-pin plastic LQFP (fine pitch) (20 x 20) * PD70F3102GJ-33-8EU * PD70F3102GJ-33-UEN VDD D0/P40 D1/P41 D2/P42 D3/P43 D4/P44 D5/P45 D6/P46 D7/P47 VSS D8/P50 D9/P51 D10/P52 D11/P53 D12/P54 D13/P55 D14/P56 D15/P57 HVDD A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5 A6/PA6 A7/PA7 VSS A8/PB0 A9/PB1 A10/PB2 A11/PB3 A12/PB4 A13/PB5 A14/PB6 A15/PB7 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 INTP103/DMARQ3/P07 INTP102/DMARQ2/P06 INTP101/DMARQ1/P05 INTP100/DMARQ0/P04 TI10/P03 TCLR10/P02 TO101/P01 TO100/P00 VSS INTP113/DMAAK3/P17 INTP112/DMAAK2/P16 INTP111/DMAAK1/P15 INTP110/DMAAK0/P14 TI11/P13 TCLR11/P12 TO111/P11 TO110/P10 INTP123/TC3/P107 INTP122/TC2/P106 INTP121/TC1/P105 INTP120/TC0/P104 TI12/P103 TCLR12/P102 TO121/P101 TO120/P100 ANI7/P77 ANI6/P76 ANI5/P75 ANI4/P74 ANI3/P73 ANI2/P72 ANI1/P71 ANI0/P70 AVDD AVSS AVREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 HVDD CS0/RAS0/P80 CS1/RAS1/P81 CS2/RAS2/P82 CS3/RAS3/P83 CS4/RAS4/IOWR/P84 CS5/RAS5/IORD/P85 CS6/RAS6/P86 CS7/RAS7/P87 LCAS/LWR/P90 UCAS/UWR/P91 RD/P92 WE/P93 BCYST/P94 OE/P95 HLDAK/P96 HLDRQ/P97 VSS REFRQ/PX5 WAIT/PX6 CLKOUT/PX7 TO150/P120 TO151/P121 TCLR15/P122 TI15/P123 INTP150/P124 INTP151/P125 INTP152/P126 2 NMI/P20 P21 TXD0/SO0/P22 RXD0/SI0/P23 SCK0/P24 TXD1/SO1/P25 RXD1/SI1/P26 SCK1/P27 VDD INTP133/SCK2/P37 INTP132/SI2/P36 INTP131/SO2/P35 INTP130/P34 TI13/P33 TCLR13/P32 TO131/P31 TO130/P30 INTP143/SCK3/P117 INTP142/SI3/P116 INTP141/SO3/P115 INTP140/P114 TI14/P113 TCLR14/P112 TO141/P111 TO140/P110 CVDD X2 X1 CVSS CKSEL MODE0 MODE1 MODE2 MODE3/VPP RESET INTP153/ADTRG/P127 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 PIN IDENTIFICATION A0 to A23: ADTRG: ANI0 to ANI7: AVDD: AVREF: AVSS: BCYST: CKSEL: CLKOUT: CS0 to CS7: CVDD: CVSS: D0 to D15: Address Bus AD Trigger Input Analog Input Analog Power Supply Analog Reference Voltage Analog Ground Bus Cycle Start Timing Clock Generator Operating Mode Select Clock Output Chip Select Clock Generator Power Supply Clock Generator Data Bus P50 to P57: P60 to P67: P70 to P77: P80 to P87: P90 to P97: P100 to P107: P110 to P117: P120 to P127: PA0 to PA7: PB0 to PB7: PX5 to PX7: RAS0 to RAS7: RD: REFRQ: RESET: RXD0, RXD1: SCK0 to SCK3: SI0 to SI3: SO0 to SO3: TC0 to TC3: TI10 to TI15: TO100, TO101, TO110, TO111, Interrupt Request from Peripherals TO120, TO121, I/O Read Strobe I/O Write Strobe Lower Column Address Strobe Lower Write Strobe Mode Output Enable Port 0 Port 1 Port 2 Port 3 Port 4 TO130, TO131, TO140, TO141, TO150, TO151: TXD0, TXD1: UCAS: VDD: VPP: VSS: WAIT: WE: X1, X2: Timer Output Transmit Data Upper Column Address Strobe Upper Write Strobe Power Supply for Internal Unit Programming Power Supply Ground Wait Write Enable Crystal Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port A Port B Port X Row Address Strobe Read Refresh Request Reset Receive Data Serial Clock Serial Input Serial Output Terminal Count Signal Timer Input DMAAK0 to DMAAK3: DMA Acknowledge DMARQ0 to DMARQ3: DMA Request HLDAK: HLDRQ: HVDD: INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153: IORD: IOWR: LCAS: LWR: MODE0 to MODE3: NMI: OE: P00 to P07: P10 to P17: P20 to P27: P30 to P37: P40 to P47: Hold Acknowledge Hold Request Power Supply for External Pins TCLR10 to TCLR15: Timer Clear Non-Maskable Interrupt Request UWR: Preliminary Data Sheet U13844EJ2V0DS00 3 PD70F3102-33 INTERNAL BLOCK DIAGRAM NMI INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 Flash memory INTC Instruction queue 128 KB PC TO100, TO101, TO110, TO111, TO120, TO121, TO130, TO131, TO140, TO141, TO150, TO151 TCLR10 to TCLR15 TI10 to TI15 4 KB Barrel shifter RPU RAM System registers Multiplier (32 x 32 64) DRAMC CPU BCU HLDRQ HLDAK CS0 to CS7/RAS0 to RAS7 IOWR IORD REFRQ BCYST WE RD Page ROM controller OE UWR/UCAS LWR/LCAS General-purpose registers (32 bits x 32) ALU DMAC SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI0 WAIT A0 to A23 D0 to D15 DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 BRG0 SO1/TXD1 SI1/RXD1 SCK1 CKSEL CLKOUT CG X1 X2 CVDD CVSS UART1/CSI1 Port BRG1 P90 to P97 P80 to P87 P70 to P77 P60 to P67 P50 to P57 P40 to P47 P30 to P37 P21 to P27 P10 to P17 PX5 to PX7 PB0 to PB7 PA0 to PA7 P120 to P127 P110 to P117 SO2 SI2 SCK2 CSI2 P100 to P107 P00 to P07 HVDD P20 BRG2 SO3 SI3 SCK3 System controller MODE0 to MODE3 RESET VPP CSI3 VDD ANI0 to ANI7 AVREF AVSS AVDD ADTRG ADC VSS 4 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 CONTENTS 1. DIFFERENCES AMONG PRODUCTS .............................................................................................. 1.1 Differences Between PD70F3102-33 and PD703102-33 ...................................................... 1.2 Differences Between PD70F3102-33 and PD70F3102A-33.................................................. 2. PIN 2.1 2.2 2.3 6 6 6 FUNCTIONS................................................................................................................................. 7 Port Pins ...................................................................................................................................... 7 Non-Port Pins .............................................................................................................................. 10 Pin I/O Circuit Types and Recommended Connection of Unused Pins ................................ 14 17 17 18 18 3. FLASH MEMORY PROGRAMMING ................................................................................................. 3.1 Selection of Communication System........................................................................................ 3.2 Flash Memory Programming Functions ................................................................................... 3.3 Connecting the Dedicated Flash Programmer......................................................................... 4. ELECTRICAL SPECIFICATIONS....................................................................................................... 19 4.1 Normal Operation Mode ............................................................................................................. 19 4.2 Flash Memory Programming Mode ........................................................................................... 74 5. PACKAGE DRAWINGS...................................................................................................................... 76 6. RECOMMENDED SOLDERING CONDITIONS................................................................................. 78 Preliminary Data Sheet U13844EJ2V0DS00 5 PD70F3102-33 1. DIFFERENCES AMONG PRODUCTS 1.1 Differences Between PD70F3102-33 and PD703102-33 Product Item Internal ROM Flash memory programming pin Flash memory programming mode PD70F3102-33 Flash memory Provided (VPP) Provided (MODE0 = L, MODE1 = H, MODE2 = L, MODE3/VPP = 7.8 V) Mask ROM None None PD703102-33 Electrical specifications Others Consumption current etc. differ (see individual data sheets). Circuit scale and master layout differ, thus noise immunity, noise radiation, etc. differ. Cautions 1. There are differences in noise immunity and noise radiation between the flash memory version and mask ROM version. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask ROM version. 2. When switching from the flash memory version to the mask ROM version, write the same code to the free area of the internal ROM. 1.2 Differences Between PD70F3102-33 and PD70F3102A-33 Product Item HVDD Electrical specifications Package 4.5 to 5.5 V PD70F3102-33 3.0 to 3.6 V PD70F3102A-33 See individual data sheets. * 144-pin plastic LQFP (fine pitch) (20 x 20) * 157-pin plastic FBGA (14 x 14) * 144-pin plastic LQFP (fine pitch) (20 x 20) 6 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 2. PIN FUNCTIONS 2.1 Port Pins (1/3) Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port 3 8-bit I/O port Input/output can be specified in 1-bit units. Input I/O Port 2 P20 is an input-only port. When a valid edge is input, it operates as an NMI input. The status of the NMI input is shown by bit 0 of register P2. P21 to P27 is a 7-bit I/O port. Input/output can be specified in 1-bit units. I/O Port 1 8-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function TO100 TO101 TCLR10 TI10 INTP100/DMARQ0 INTP101/DMARQ1 INTP102/DMARQ2 INTP103/DMARQ3 TO110 TO111 TCLR11 TI11 INTP110/DMAAK0 INTP111/DMAAK1 INTP112/DMAAK2 INTP113/DMAAK3 NMI - TXD0/SO0 RXD0/SI0 SCK0 TXD1/SO1 RXD1/SI1 SCK1 TO130 TO131 TCLR13 TI13 INTP130 INTP131/SO2 INTP132/SI2 INTP133/SCK2 D0 to D7 Preliminary Data Sheet U13844EJ2V0DS00 7 PD70F3102-33 (2/3) Pin Name P50 to P57 I/O I/O Function Port 5 8-bit I/O port Input/output can be specified in 1-bit units. Port 6 8-bit I/O port Input/output can be specified in 1-bit units. Port 7 8-bit input-only port Port 8 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function D8 to D15 P60 to P67 I/O A16 to A23 P70 to P77 Input ANI0 to ANI7 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 P94 P95 P96 P97 P100 P101 P102 P103 P104 P105 P106 P107 I/O CS0/RAS0 CS1/RAS1 CS2/RAS2 CS3/RAS3 CS4/RAS4/IOWR CS5/RAS5/IORD CS6/RAS6 CS7/RAS7 I/O Port 9 8-bit I/O port Input/output can be specified in 1-bit units LCAS/LWR UCAS/UWR RD WE BCYST OE HLDAK HLDRQ I/O Port 10 8-bit I/O port Input/output can be specified in 1-bit units. TO120 TO121 TCLR12 TI12 INTP120/TC0 INTP121/TC1 INTP122/TC2 INTP123/TC3 8 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (3/3) Pin Name P110 P111 P112 P113 P114 P115 P116 P117 P120 P121 P122 P123 P124 P125 P126 P127 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PX5 PX6 PX7 I/O Port X 3-bit I/O port Input/output can be specified in 1-bit units. I/O Port B 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port A 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port 12 8-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Function Port 11 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function TO140 TO141 TCLR14 TI14 INTP140 INTP141/SO3 INTP142/SI3 INTP143/SCK3 TO150 TO151 TCLR15 TI15 INTP150 INTP151 INTP152 INTP153/ADTRG A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 REFRQ WAIT CLKOUT Preliminary Data Sheet U13844EJ2V0DS00 9 PD70F3102-33 2.2 Non-Port Pins (1/4) Pin Name TO100 TO101 TO110 TO111 TO120 TO121 TO130 TO131 TO140 TO141 TO150 TO151 TCLR10 TCLR11 TCLR12 TCLR13 TCLR14 TCLR15 TI10 TI11 TI12 TI13 TI14 TI15 INTP100 INTP101 INTP102 INTP103 INTP110 INTP111 INTP112 INTP113 INTP120 INTP121 INTP122 INTP123 Input External maskable interrupt request input, or timer 12 external capture trigger input Input External maskable interrupt request input, or timer 11 external capture trigger input Input External maskable interrupt request input, or timer 10 external capture trigger input Input External count clock input of timers 10 to 15 Input External clear signal input of timers 10 to 15 I/O Output Function Pulse signal output of timers 10 to 15 Alternate Function P00 P01 P10 P11 P100 P101 P30 P31 P110 P111 P120 P121 P02 P12 P102 P32 P112 P122 P03 P13 P103 P33 P113 P123 P04/DMARQ0 P05/DMARQ1 P06/DMARQ2 P07/DMARQ3 P14/DMAAK0 P15/DMAAK1 P16/DMAAK2 P17/DMAAK3 P104/TC0 P105/TC1 P106/TC2 P107/TC3 10 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (2/4) Pin Name INTP130 INTP131 INTP132 INTP133 INTP140 INTP141 INTP142 INTP143 INTP150 INTP151 INTP152 INTP153 SO0 SO1 SO2 SO3 SI0 SI1 SI2 SI3 SCK0 SCK1 SCK2 SCK3 TXD0 TXD1 RXD0 RXD1 D0 to D7 D8 to D15 A0 to A7 A8 to A15 A16 to A23 LWR UWR RD WE OE Output Output Output Output Output External data bus lower byte write enable signal output External data bus upper byte write enable signal output External data bus read strobe signal output Write enable signal output for DRAM Output enable signal output for DRAM Output 24-bit address bus for external memory I/O 16-bit data bus for external memory Input UART0 and UART1 serial reception data input Output UART0 and UART1 serial transmission data output I/O CSI0 to CSI3 serial clock input/output (3-wire) Input CSI0 to CSI3 serial reception data input (3-wire) Output CSI0 to CSI3 serial transmission data output (3-wire) Input External maskable interrupt request input, or timer 15 external capture trigger input Input External maskable interrupt request input, or timer 14 external capture trigger input I/O Input Function External maskable interrupt request input, or timer 13 external capture trigger input Alternate Function P34 P35/SO2 P36/SI2 P37/SCK2 P114 P115/SO3 P116/SI3 P117/SCK3 P124 P125 P126 P127/ADTRG P22/TXD0 P25/TXD1 P35/INTP131 P115/INTP141 P23/RXD0 P26/RXD1 P36/INTP132 P116/INTP142 P24 P27 P37/INTP133 P117/INTP143 P22/SO0 P25/SO1 P23/SI0 P26/SI1 P40 to P47 P50 to P57 PA0 to PA7 PB0 to PB7 P60 to P67 P90/LCAS P91/UCAS P92 P93 P95 Preliminary Data Sheet U13844EJ2V0DS00 11 PD70F3102-33 (3/4) Pin Name LCAS UCAS RAS0 to RAS3 RAS4 RAS5 RAS6 RAS7 BCYST CS0 to CS3 Output Output Strobe signal output indicating start of bus cycle Chip select signal output I/O Output Output Output Function Column address strobe signal output for lower data of DRAM Column address strobe signal output for higher data of DRAM Row address strobe signal output for DRAM Alternate Function P90/LWR P91/UWR P80/CS0 to P83/CS3 P84/CS4/IOWR P85/CS5/IORD P86/CS6 P87/CS7 P94 P80/RAS0 to P83/RAS3 P84/RAS4/IOWR P85/RAS5/IORD P86/RAS6 P87/RAS7 Input Output Output Output Input Control signal input that inserts a wait in the bus cycle Refresh request signal output for DRAM DMA write strobe signal output DMA read strobe signal output DMA request signal input PX6 PX5 P84/RAS4/CS4 P85/RAS5/CS5 P04/INTP100 to P07/INTP103 P14/INTP110 to P17/INTP113 P104/INTP120 to P107/INTP123 P96 P97 P70 to P77 P20 PX7 - - CS4 CS5 CS6 CS7 WAIT REFRQ IOWR IORD DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 TC0 to TC3 Output DMA acknowledge signal output Output DMA termination (terminal count) signal output HLDAK HLDRQ ANI0 to ANI7 NMI CLKOUT CKSEL MODE0 to MODE2 MODE3 RESET X1 X2 ADTRG AVREF AVDD Output Input Input Input Output Input Input Bus hold acknowledge output Bus hold request input Analog input to A/D converter Non-maskable interrupt request input System clock output Input that specifies the clock generator's operation mode Operation mode specification VPP Input Input - Input Input - System reset input Connecting system clock resonator. In the case of an external clock, it is input to X1. A/D converter external trigger input Reference voltage applied to A/D converter Positive power supply for A/D converter - - - P127/INTP153 - - 12 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (4/4) Pin Name AVSS CVDD CVSS VDD HVDD VSS VPP I/O - - - - - - - Function Ground potential for A/D converter Positive power supply for the dedicated clock generator Ground potential for dedicated clock generator Positive power supply (internal unit power supply) Positive power supply (external pin power supply) Ground potential High-voltage application pin during program write/verify MODE3 Alternate Function - - - - - - Preliminary Data Sheet U13844EJ2V0DS00 13 PD70F3102-33 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins, and Figure 2-1 shows the schematic circuit diagram for each I/O circuit type. In the case of connection to VDD or VSS via a resistor, connection of a resistor of 1 to 10 k is recommended. Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2) I/O Circuit Type 5 5-K Input: Pin P00/TO100, P01/TO101 P02/TCLR10, P03/TI10 P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3 P10/TO110, P11/TO111 P12/TCLR11, P13/TI11 P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3 P20/NMI P21 P22/TXD0/SO0 P23/RXD0/SI0 P24/SCK0 P25/TXD1/SO1 P26/RXD1/SI1 P27/SCK1 P30/TO130, P31/TO131 P32/TCLR13, P33/TI13 P34/INTP130 P35/INTP131/SO2 P36/INTP132/SI2 P37/INTP133/SCK2 P40/D0 to P47/D7 P50/D8 to P57/D15 P60/A16 to P67/A23 P70/ANI0 to P77/ANI7 Recommended Connection of Unused Pins Independently connect to HVDD or VSS via a resistor. Output: Leave open. 5 5-K 2 5 Connect directly to VSS. Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. 5-K 5 5-K 5 5-K 5 9 Connect directly to VSS. 14 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2) I/O Circuit Type 5 Pin P80/CS0/RAS0 to P83/CS3/RAS3 P84/CS4/RAS4/IOWR, P85/CS5/RAS5/IORD P86/CS6/RAS6, P87/CS7/RAS7 P90/LCAS/LWR P91/UCAS/UWR P92/RD P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P100/TO120, P101/TO121 P102/TCLR12, P103/TI12 P104/INTP120/TC0 to P107/INTP123/TC3 P110/TO140, P111/TO141 P112/TCLR14, P113/TI14 P114/INTP140 P115/INTP141/SO3 P116/INTP142/SI3 P117/INTP143/SCK3 P120/TO150, P121/TO151 P122/TCLR15, P123/TI15 P124/INTP150 to P126/INTP152 P127/INTP153/ADTRG PA0/A0 to PA7/A7 PB0/A8 to PB7/A15 PX5/REFRQ PX6/WAIT PX7/CLKOUT CKSEL RESET MODE0 to MODE2 MODE3/VPP AVREF, AVSS AVDD Recommended Connection of Unused Pins Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. 5 5-K Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. 5 5-K 5 5-K 5 1 2 Connect directly to HVDD. - Connect to VSS via a resistor (RVPP). - - Connect directly to VSS. Connect directly to HVDD. Preliminary Data Sheet U13844EJ2V0DS00 15 PD70F3102-33 Figure 2-1. Pin Input/Output Circuits Type 1 Type 5-K VDD VDD Data P-ch IN Output disable N-ch N-ch P-ch IN/OUT Input enable Type 2 Type 9 P-ch IN IN N-ch + - Comparator VREF (threshold voltage) Input enable Schmitt-triggered input with hysteresis characteristics Type 5 VDD Data P-ch IN/OUT Output disable N-ch Input enable Caution Replace VDD in the circuit diagrams with HVDD. 16 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 3. FLASH MEMORY PROGRAMMING The following two flash memory programming methods are available. (1) On-board programming The program is written to the flash memory using a dedicated flash programmer after the PD70F3102-33 is mounted on the target board. Install the connectors, etc., required for communication with the dedicated flash programmer, on the target board. (2) Off-board programming The program is written to the flash memory using a dedicated adapter before the PD70F3102-33 is mounted on the target board. 3.1 Selection of Communication System Writing to the flash memory is done via serial communication using the dedicated flash programmer. Select one of the communication modes listed in Table 3-1. Base your selection of the communication mode on the selection format shown in Table 3-1. Refer to the number of VPP pulses shown in Table 3-1 when selecting the communication mode. Table 3-1. Communication Modes Communication Mode CSI0 SO0 (serial data output) SI0 (serial data input) SCK0 (serial clock input) TXD0 (serial data output) RXD0 (serial data input) Pins Used Number of VPP Pulses 0 UART0 8 Figure 3-1. Communication Mode Selection Format 7.8 V VPP VDD VSS VDD RESET VSS Preliminary Data Sheet U13844EJ2V0DS00 17 PD70F3102-33 3.2 Flash Memory Programming Functions Flash memory programming is performed by sending and receiving commands and data according to the selected communication mode. Table 3-2 shows the main flash memory programming functions. Table 3-2. Main Flash Memory Programming Functions Function Batch erasure Batch blank check Data write Batch verify Erases the contents of the entire memory. Checks whether the entire memory has been erased. Writes data to flash memory based on the write start address and the number of bytes to be written. Compares the contents of the entire memory with the input data. Description 3.3 Connecting the Dedicated Flash Programmer The connection of the dedicated flash programmer to the PD70F3102-33 differs depending on the communication mode. Figures 3-2 and 3-3 show the various connection types. Figure 3-2. Connection of Dedicated Flash Programmer for CSI0 Mode Dedicated flash programmer CLK VPP VDD RESET SCK SO SI VSS PD70F3102-33 CLK VPP VDD RESET SCK0 SI0 SO0 VSS Figure 3-3. Connection of Dedicated Flash Programmer for UART0 Mode Dedicated flash programmer CLK VPP VDD RESET TxD RxD VSS PD70F3102-33 CLK VPP VDD RESET RXD0 TXD0 VSS 18 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 4. ELECTRICAL SPECIFICATIONS 4.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD HVDD CVDD CVSS AVDD AVSS Input voltage VI VDD pin HVDD pin, HVDD VDD CVDD pin CVSS pin AVDD pin AVSS pin Except X1 pin, MODE3/VPP pin MODE3/VPP pin MODE3/VPP pin in flash memory programming mode Clock input voltage Output current, low VK IOL X1, VDD = 3.0 to 3.6 V 1 pin Total of all pins Output current, high IOH 1 pin Total of all pins Output voltage Analog input voltage VO VIAN HVDD = 5.0 V 10% P70/ANI0 to P77/ANI7 pins AVDD > HVDD HVDD AVDD TA Tstg AVDD > HVDD HVDD AVDD Conditions Ratings -0.5 to +4.6 -0.5 to +7.0 -0.5 to +4.6 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to +0.5 -0.5 to HVDD + 0.5 -0.5 to VDD + 0.5 -0.5 to +11.0 Unit V V V V V V V V V -0.5 to VDD + 1.0 4.0 100 -4.0 -100 -0.5 to HVDD + 0.5 -0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5 -0.5 to HVDD + 0.5 -0.5 to AVDD + 0.5 -40 to +85 -65 to +125 V mA mA mA mA V V V V V C C A/D converter reference input voltage Operating ambient temperature Storage temperature AVREF Cautions 1. Do not directly connect output pins (or I/O pins) of IC products, and do not connect them directly to VDD, VCC, or GND. However, open-drain pins and open-collector pins can be directly connected to each other. Moreover, external circuits that implement a timing that avoids conflict with the output of pins that go into high-impedance can be directly connected. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Preliminary Data Sheet U13844EJ2V0DS00 19 PD70F3102-33 Capacitance (TA = 25C, VDD = HVDD = CVDD = VSS = 0 V) Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF Operating Conditions Operation Mode Direct mode Internal Operation Clock Frequency () 10 to 33 MHz Note Operating Ambient Temperature (TA) -40 to +85C Supply Voltage (VDD, HVDD) VDD = 3.0 to 3.6 V, HVDD = 5.0 V 10% VDD = 3.0 to 3.6 V, HVDD = 5.0 V 10% PLL mode 20 to 33 MHz -40 to +85C Note Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz. 20 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 Recommended Oscillator (a) Connection of ceramic resonator (TA = -40 to +85C) (i) Murata Mfg. Co., Ltd. (TA = -40 to +85C) X1 X2 Rd C1 C2 Type Product Name Oscillation Frequency fXX (MHz) 4.0 4.0 5.0 5.0 6.6 6.6 8.0 8.0 4.0 4.0 5.0 5.0 6.6 6.6 8.0 8.0 Recommended Circuit Constant C1 (pF) 100 On-chip 100 On-chip 30 On-chip 30 On-chip 100 On-chip 100 On-chip 30 On-chip 30 On-chip C2 (pF) 100 On-chip 100 On-chip 30 On-chip 30 On-chip 100 On-chip 100 On-chip 30 On-chip 30 On-chip Rd (k) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Oscillation Voltage Range MIN. (V) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 Oscillation Stabilization Time (MAX.) TOST (ms) MAX. (V) 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.5 0.3 0.4 0.2 0.2 0.1 0.2 0.3 0.5 0.5 0.5 0.5 0.1 0.1 0.1 0.1 Surface mount CSAC4.00MGC040 CSTCC4.00MG0H6 CSAC5.00MGC040 CSTCC5.00MG0H6 CSAC6.60MT CSTCC6.60MG0H6 CSAC8.00MT CSTCC8.00MG0H6 Lead CSA4.00MG040 CST4.00MGW040 CSA5.00MG040 CST5.00MGW040 CSA6.60MTZ CST6.60MTW CSA8.00MTZ CST8.00MTW Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the PD70F3102-33 and the resonator. Preliminary Data Sheet U13844EJ2V0DS00 21 PD70F3102-33 (ii) TDK Corporation (TA = -40 to +85C) X1 X2 Rd C1 C2 Manufacturer Product Name Oscillation Frequency fXX (MHz) 4.0 5.0 8.0 Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip Rd (k) 0 0 0 Oscillation Voltage Range MIN. (V) 3.0 3.0 3.0 Oscillation Stabilization Time (MAX.) TOST (ms) MAX. (V) 3.6 3.6 3.6 0.17 0.15 0.11 TDK CCR4.0MC3 CCR5.0MC3 CCR8.0MC5 Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the PD70F3102-33 and the resonator. (iii) Kyocera Corporation (TA = -20 to +80C) X1 X2 Rd C1 C2 Manufacturer Product Name Oscillation Frequency fXX (MHz) 5.0 6.0 6.6 Recommended Circuit Constant C1 (pF) On-chip On-chip On-chip C2 (pF) On-chip On-chip On-chip Rd (k) 0 0 0 Oscillation Voltage Range MIN. (V) 3.0 3.0 3.0 Oscillation Stabilization Time (MAX.) TOST (ms) MAX. (V) 3.6 3.6 3.6 0.06 0.06 0.06 Kyocera PBRC5.00BR-A PBRC6.00BR-A PBRC6.60BR-A Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the PD70F3102-33 and the resonator. 22 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (b) External clock input (TA = -40 to +85C) X1 X2 Open External clock Caution Input a CMOS level voltage to the X1 pin. Cautions when turning on/off the power The PD70F3102-33 is configured with power supply pins for the internal unit (VDD) and for the external pins (HVDD). The operation guaranteed range is VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%. The input and output state of ports may be undefined when the voltage exceeds this range. Preliminary Data Sheet U13844EJ2V0DS00 23 PD70F3102-33 DC Characteristics (TA = -40 to 85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V) Parameter Input voltage, high Symbol VIH Conditions Except Note 1 Note 1 Input voltage, low VIL Except Notes 1 and 2 Note 1 Clock input voltage, high VXH X1 pin Direct mode PLL mode Clock input voltage, low VXL X1 pin Direct mode PLL mode Schmitt-triggered input threshold voltage Schmitt-triggered input hysteresis width Output voltage, high HVT HVT + MIN. 2.2 0.8HVDD -0.5 -0.5 0.8VDD 0.8VDD -0.3 -0.3 TYP. MAX. HVDD + 0.3 HVDD + 0.3 +0.8 0.2HVDD VDD + 0.3 VDD + 0.3 0.15VDD 0.15VDD Unit V V V V V V V V V V V Note 1, rising edge Note 1, falling edge Note 1 0.5 3.0 2.0 - HVT - -HVT VOH + IOH = -2.5 mA IOH = -100 A 0.7HVDD HVDD - 0.4 0.45 10 -10 10 -10 V V V Output voltage, low, Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low VOL ILIH ILIL ILOH ILOL IOL = 2.5 mA VI = HVDD, except Note 2 VI = 0 V, except Note 2 VO = HVDD VO = 0 V A A A A Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET 2. When using the P70/AN10 to P77/ANI7 pins as analog inputs. Remark TYP. values are reference values for when TA = 25C, VDD = CVDD = 3.3 V, HVDD = 5.0 V. 24 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 DC Characteristics (TA = -40 to 85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V) Parameter Supply current During normal Symbol IDD1 Conditions Direct mode VDD + CVDD HVDD PLL mode VDD + CVDD MIN. TYP. 2.0 x fX 1.8 x fX 2.7 x fX - 17.0 1.3 x fX - 3.6 1.4 x fX 0.8 x fX 1.8 x fX - 10.0 0.8 x fX - 1.0 3.0 0.5 3.0 0.5 20 20 10 MAX. 4.5 x fX 3.0 x fX 4.5 x fX 3.0 x fX 3.0 x fX 1.5 x fX 3.0 x fX 1.5 x fX Unit mA mA mA HVDD mA During HALT IDD2 Direct mode VDD + CVDD HVDD mA mA mA PLL mode VDD + CVDD HVDD mA During IDLE IDD3 Direct mode VDD + CVDD HVDD 10 1.0 10 1.0 50 600 20 mA mA mA mA PLL mode VDD + CVDD HVDD During STOP IDD4 VDD + CVDD -40C TA +40C +40C < TA +85C A A A HVDD Remarks 1. TYP. values are reference values for when TA = 25C, VDD = CVDD = 3.3 V, HVDD = 5.0 V. 2. Direct mode: fX = 10 to 33 MHz PLL mode: fX = 20 to 33 MHz 3. The fX unit is MHz. Preliminary Data Sheet U13844EJ2V0DS00 25 PD70F3102-33 Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention voltage Symbol VDDDR HVDDDR Data retention current IDDDR Conditions STOP mode, VDD = VDDDR STOP mode, HVDD = HVDDDR VDD = VDDDR -40C TA +40C +40C < TA +85C MIN. 1.5 VDDDR TYP. MAX. 3.6 5.5 50 600 Unit V V A A s s ms Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage tRVD tFVD tHVD 200 200 0 tDREL VIHDR Note 0 0.8HVDDDR HVDDDR ns V VILDR Note 0 0.2HVDDDR V Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET Remark TYP. values are reference values for when TA = 25C. STOP mode setting VDD tFVD tHVD HVDD VDDDR tRVD tDREL RESET (input) VIHDR NMI (input) (released by falling edge) VIHDR NMI (input) (released by rising edge) VILDR 26 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 AC Characteristics (TA = -40 to +85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V, Output Pin Load Capacitance: CL = 50 pF) AC Test Input Waveforms (a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P114/INTP140, P36/INTP132/SI2, P37/INTP133/SCK2, P116/INTP142/SI3, P104/INTP120/TC0 to P107/INTP123/TC3, P115/INTP141/SO3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET HVDD Input signal 0V 0.2HVDD 0.8HVDD Measurement points 0.8HVDD 0.2HVDD (b) Other than (a) 2.4 V Input signal 0.4 V 0.8 V 2.2 V 2.2 V 0.8 V Measurement points AC Test Output Measurement Points 2.4 V Output signal 0.8 V Measurement points 2.4 V 0.8 V Load Conditions DUT (Device under test) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. Preliminary Data Sheet U13844EJ2V0DS00 27 PD70F3102-33 (1) Clock timing Parameter X1 input cycle Symbol <1> tCYX Conditions In direct mode In PLL mode X1 input high-level width <2> tWXH In direct mode In PLL mode X1 input low-level width <3> tWXL In direct mode In PLL mode X1 input rise time <4> tXR In direct mode In PLL mode X1 input fall time <5> tXF In direct mode In PLL mode CPU operating frequency CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time - <6> <7> <8> <9> <10> MIN. 15 150 5 50 5 50 4 10 4 10 10 30 0.5T - 7 0.5T - 4 5 5 33 100 MAX. 250 250 Unit ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns tCYK tWKH tWKL tKR tKF Remark T = tCYK <1> <2> <4> X1 (PLL mode) <1> <2> <4> X1 (Direct mode) <5> <3> <5> <3> CLKOUT (output) <9> <7> <6> <10> <8> 28 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (2) Output waveform (other than X1, CLKOUT) Parameter Output rise time Output fall time Symbol <12> <13> tOR tOF Conditions MIN. MAX. 10 10 Unit ns ns <12> <13> Signals other than X1, CLKOUT (3) Reset timing Parameter RESET pin high-level width RESET pin low-level width Symbol <14> <15> tWRSH tWRSL Conditions MIN. 500 MAX. Unit ns ns ns At power ON, STOP mode release Except at power ON, STOP mode release 500 + TOS 500 Remark TOS: Oscillation stabilization time <14> <15> RESET (input) Preliminary Data Sheet U13844EJ2V0DS00 29 PD70F3102-33 (4) SRAM, external ROM, external I/O access timing (a) Access timing (SRAM, external ROM, external I/O) (1/2) Parameter Address, CSn output delay time (from CLKOUT) Address, CSn output hold time (from CLKOUT) RD, IORD delay time (from CLKOUT) RD, IORD delay time (from CLKOUT) UWR, LWR, IOWR delay time (from CLKOUT) UWR, LWR, IOWR delay time (from CLKOUT) BCYST delay time (from CLKOUT) BCYST delay time (from CLKOUT) WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time (from CLKOUT) Data output hold time (from CLKOUT) Symbol <16> tDKA Conditions MIN. 2 MAX. 10 Unit ns <17> tHKA 2 10 ns <18> tDKRDL 2 14 ns <19> tHKRDH 2 14 ns <20> tDKWRL 2 10 ns <21> tHKWRH 2 10 ns <22> tDKBSL 2 10 ns <23> tHKBSH 2 10 ns <24> <25> <26> tSWK tHKW tSKID 15 2 18 ns ns ns <27> tHKID 2 ns <28> tDKOD 2 10 ns <29> tHKOD 2 10 ns Remarks 1. Observe at least one of the data input hold times, tHKID or tHRDID. 2. n = 0 to 7 30 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (a) Access timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) <16> <17> A0 to A23 (Output) CSn (Output) <22> <23> BCYST (Output) <18> <19> RD, IORD (Output) [Read time] <20> <21> UWR, LWR, IOWR (Output) [Write time] <26> <27> D0 to 15 (I/O) [Read time] <28> <29> D0 to 15 (I/O) [Write time] <25> <24> <24> <25> WAIT (Input) Remarks 1. Timing when number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 31 PD70F3102-33 (b) Read timing (SRAM, external ROM, external I/O) (1/2) Parameter Data input setup time (to address) Data input setup time (to RD) RD, IORD low-level width RD, IORD high-level width Delay time from address, CSn to RD, IORD Delay time from RD, IORD to address Data input hold time (from RD, IORD) Delay time from RD, IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) <37> tDRDOD (0.5 + i) T - 10 ns Symbol <30> <31> <32> <33> <34> tSAID tSRDID tWRDL tWRDH tDARD (1 + wD + w) T - 10 T - 10 0.5T - 10 Conditions MIN. MAX. (1.5 + wD + w) T - 28 (1 + wD +w) T - 32 Unit ns ns ns ns ns <35> tDRDA (0.5 + i) T - 10 ns <36> tHRDID 0 ns <38> <39> <40> tSAW tSBSW tHBSW Note Note Note 0 T - 25 T - 25 ns ns ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1, DWC2 4. i: Number of idle states inserted when a write cycle follows the read cycle. 5. Observe at least one of the data input hold times, tHKID or tHRDID. 6. n = 0 to 7 32 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (b) Read timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) UWR, LWR, IOWR (Output) <33> <32> <35> RD, IORD (Output) <34> <31> <30> <36> <37> D0 to D15 (I/O) <38> WAIT (Input) <39> <40> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 33 PD70F3102-33 (c) Write timing (SRAM, external ROM, external I/O) (1/2) Parameter WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) Delay time from address, CSn to UWR, LWR, IOWR Address setup time (to UWR, LWR, IOWR) Delay time from UWR, LWR, IOWR to address UWR, LWR, IOWR high-level width UWR, LWR, IOWR low-level width Data output setup time (to UWR, LWR, IOWR) Data output hold time (from UWR, LWR, IOWR) Symbol <38> <39> <40> <41> tSAW tSBSW tHBSW tDAWR Conditions Note Note Note 0 0.5T - 10 MIN. MAX. T - 25 T - 25 Unit ns ns ns ns <42> tSAWR (1.5 + wD + w) T - 10 ns <43> tDWRA 0.5T - 10 ns <44> tWWRH T - 10 ns <45> <46> tWWRL tSODWR (1 + wD + w) T - 10 (1.5 + wD + w) T - 10 ns ns <47> tHWROD 0.5T - 10 ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2 4. n = 0 to 7 34 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (c) Write timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) RD, IORD (Output) <42> <45> <43> <41> <44> UWR, LWR, IOWR (Output) <46> <47> D0 to D15 (I/O) <38> WAIT (Input) <39> <40> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 35 PD70F3102-33 (d) DMA flyby transfer timing (SRAM external I/O transfer) (1/2) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) RD low-level width RD high-level width Delay time from address, CSn to RD Delay time from RD to address Delay time from RD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) Delay time from address to IOWR Address setup time (to IOWR) Delay time from IOWR to address IOWR high-level width IOWR low-level width Delay time from IOWR to RD Symbol <24> <25> <32> <33> <34> tSWK tHKW tWRDL tWRDH tDARD Conditions MIN. 15 2 (1 + wD + wF + w) T - 10 T - 10 0.5T - 10 MAX. Unit ns ns ns ns ns <35> <37> tDRDA tDRDOD (0.5 + i) T - 10 (0.5 + i) T - 10 ns ns <38> <39> <40> <41> tSAW tSBSW tHBSW tDAWR Note Note Note 0 0.5T - 10 T - 25 T - 25 ns ns ns ns <42> <43> tSAWR tDWRA (1.5 + wD + w) T - 10 0.5T - 10 ns ns <44> <45> <48> tWWRH tWWRL tDWRRD wF = 0 wF = 1 T - 10 (1 + wD + w) T - 10 0 T - 10 0.5T - 10 ns ns ns ns ns Delay time from DMAAKm to IOWR Delay time from IOWR to DMAAKm <49> tDDAWR <50> tDWRDA (0.5 + wF) T - 10 ns Note During the first WAIT sampling, when number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1, DWC2 4. wF: Number of waits inserted to source-side access during DMA flyby transfer 5. i: Number of idle states inserted when a write cycle follows the read cycle 6. n = 0 to 7, m = 0 to 3 36 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (d) DMA flyby transfer timing (SRAM external I/O transfer) (2/2) T1 CLKOUT (Output) TW T2 A0 to A23 (Output) CSn (Output) <33> <32> <35> RD (Output) <34> <48> UWR, LWR (Output) DMAAKm (Output) <49> <50> IORD (Output) <42> <41> <44> IOWR (Output) <45> <43> <37> D0 to D15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25> Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Preliminary Data Sheet U13844EJ2V0DS00 37 PD70F3102-33 (e) DMA flyby transfer timing (external I/O SRAM transfer) (1/2) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) IORD low-level width IORD high-level width Delay time from address, CSn to IORD Delay time from IORD to address Delay time from IORD to data output WAIT setup time (to address) WAIT setup time (to BCYST) WAIT hold time (from BCYST) Delay time from address to UWR, LWR Address setup time (to UWR, LWR) Delay time from UWR, LWR to address UWR, LWR high-level width UWR, LWR low-level width Delay time from UWR, LWR to IORD Delay time from DMAAKm to IORD Delay time from IORD to DMAAKm Symbol <24> <25> <32> <33> <34> tSWK tHKW tWRDL tWRDH tDARD Conditions MIN. 15 2 (1 + wD + wF + w) T - 10 T - 10 0.5T - 10 MAX. Unit ns ns ns ns ns <35> <37> tDRDA tDRDOD (0.5 + i) T - 10 (0.5 + i) T - 10 ns ns <38> <39> <40> <41> tSAW tSBSW tHBSW tDAWR Note Note Note 0 0.5T - 10 T - 25 T - 25 ns ns ns ns <42> tSAWR (1.5 + wD + w) T - 10 ns <43> tDWRA 0.5T - 10 ns <44> <45> <48> tWWRH tWWRL tDWRRD wF = 0 wF = 1 T - 10 (1 + wD + w) T - 10 0 T - 10 0.5T - 10 ns ns ns ns ns <51> tDDARD <52> tDRDDA 0.5T - 10 ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2. 4. wF: Number of waits inserted to source-side access during DMA flyby transfer. 5. i: Number of idle states inserted when a write cycle follows the read cycle. 6. n = 0 to 7, m = 0 to 3 38 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (e) DMA flyby transfer timing (external I/O SRAM transfer) (2/2) T1 CLKOUT (Output) TW T2 A0 to A23 (Output) CSn (Output) <41> <44> UWR, LWR (Output) <42> <45> <43> <48> RD (Output) <51> <52> DMAAKm (Output) IOWR (Output) <34> <33> IORD (Output) <32> <35> <37> D0 to D15 (I/O) <38> <24> WAIT (Input) <40> <39> BCYST (Output) <25> <24> <25> Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0 and wF = 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Preliminary Data Sheet U13844EJ2V0DS00 39 PD70F3102-33 (5) Page ROM access timing (1/2) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Off-page data input setup time (to address) Off-page data input setup time (to RD) Off-page RD low-level width RD high-level width Data input hold time (from RD) Delay time from RD to data output On-page RD low-level width On-page data input setup time (to address) On-page data input setup time (to RD) Symbol <24> <25> <26> tSWK tHKW tSKID Conditions MIN. 15 2 18 MAX. Unit ns ns ns <27> tHKID 2 ns <30> tSAID (1.5 + wD +w) T - 28 ns <31> tSRDID (1 + wD + w) T - 32 ns <32> <33> <36> <37> tWRDL tWRDH tHRDID tDRDOD (1 + wD + w) T - 10 0.5T - 10 0 (0.5 + i) T - 10 ns ns ns ns <53> <54> tWORDL tSOAID (1.5 + wPR + w) T - 10 (1.5 + wPR + w) T - 28 ns ns <55> tSORDID (1.5 + wPR + w) T - 32 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2. 4. wPR: Number of waits specified by register PRC. 5. i: Number of idle states inserted when a write cycle follows the read cycle. 6. Observe at least one of the data input hold times, tHKID or tHRDID. 40 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (5) Page ROM access timing (2/2) T1 CLKOUT (Output) TDW TW T2 TO1 TPRW TW TO2 Off-page address Note CSn (Output) On-page address Note <26> <30> UWR, LWR (Output) <33> <32> <31> RD (Output) <36> <26> <27> D0 to D15 (I/O) <25> <24> WAIT (Input) <24> <25> <24> <25> <24> <25> <27> <36> <53> <55> <37> <54> BCYST (Output) Note On-page addresses and off-page addresses are as follows. PRC Register On-Page Addresses MA5 0 0 0 1 MA4 0 0 1 1 MA3 0 1 1 1 A0, A1 A0 to A2 A0 to A3 A0 to A4 A2 to A23 A3 to A23 A4 to A23 A5 to A23 Off-Page Addresses Remarks 1. These timings are for the following cases: Number of waits (TDW) specified by registers DWC1 and DWC2: 1 Number of waits (TPRW) specified by register PRC: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 41 PD70F3102-33 (6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from OE to data output Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time Symbol <24> <25> <26> <27> <37> <56> <57> <58> <59> <60> tSWK tHKW tSKID tHKID tDRDOD tASR tRAH tASC tCAH tRC Conditions MIN. 15 2 18 2 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + w) T - 10 (3 + wRP + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (2.5 + wRH + wDA + w) T - 10 (1.5 + wDA + w) T - 10 (2 + wDA + w) T - 10 (1 + wDA + w) T - 10 (1 + wRP) T - 10 (2 + wRH + wDA + w) T - 10 (2 + wRP + wRH) T - 10 0.5T - 10 T - 10 (2 + wRP + wRH) T - 10 (2 + wRP + wRH + wDA + w) T - 28 (2 + wRH + wDA + w) T - 28 (1.5 + wDA + w) T - 28 (1 + wDA + w) T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns RAS recharge time RAS pulse time <61> <62> tRP tRAS ns ns RAS hold time Column address read time for RAS CAS pulse width CAS to RAS precharge time CAS hold time WE setup time WE hold time (from RAS) WE hold time (from CAS) CAS precharge time Output enable access time <63> <64> <65> <66> <67> <68> <69> <70> <71> <72> tRSH tRAL tCAS tCRP tCSH tRCS tRRH tRCH tCPN tOEA ns ns ns ns ns ns ns ns ns ns RAS access time Access time from column address CAS access time <73> <74> <75> tRAC tAA tCAC ns ns ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: Number of idle states inserted when a write cycle follows the read cycle. 42 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3) Parameter RAS column address delay time RAS to CAS delay time Output buffer turn off delay time (from OE) Output buffer turn off delay time (from CAS) Symbol <76> <77> <78> tRAD tRCD tOEZ Conditions MIN. (0.5 + wRH) T - 10 (1 + wRH) T - 10 0 MAX. Unit ns ns ns <79> tOFF 0 ns Remarks 1. T = tCYK 2. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) Preliminary Data Sheet U13844EJ2V0DS00 43 PD70F3102-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3) TRPW CLKOUT (Output) <58> <56> <57> <59> T1 TRHW T2 TDAW TW T3 A0 to A23 (Output) Row address Column address <63> <64> <62> <76> <61> RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <73> <68> <75> <70> <69> <67> <65> WE (Output) <74> <72> <27> <37> <79> OE (Output) <78> <26> D0 to D15 (I/O) <24> <25> <24> <25> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 44 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 [MEMO] Preliminary Data Sheet U13844EJ2V0DS00 45 PD70F3102-33 (b) Read timing (high-speed DRAM access: on-page) (1/2) Parameter Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from OE to data output Column address setup time Column address hold time RAS hold time Column address read time for RAS CAS pulse width WE setup time (to CAS) WE hold time (from RAS) WE hold time (from CAS) Output enable access time Access time from column address CAS access time Output buffer turn-off delay time (from OE) Output buffer turn-off delay time (from CAS) Access time from CAS precharge CAS precharge time High-speed page mode cycle time RAS hold time from CAS precharge Symbol <26> <27> <37> <58> <59> <63> <64> <65> <68> <69> <70> <72> <74> <75> <78> tSKID tHKID tDRDOD tASC tCAH tRSH tRAL tCAS tRCS tRRH tRCH tOEA tAA tCAC tOEZ 0 Conditions MIN. 18 2 (0.5 + i) T - 10 (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA) T - 10 (1 + wCP) T - 10 0.5 T - 10 T - 10 (1 + wCP + wDA) T - 28 (1.5 + wCP + wDA) T - 28 (1 + wDA) T - 28 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns <79> tOFF 0 ns <80> <81> <82> <83> tACP tCP tPC tRHCP (1 + wCP) T - 10 (2 + wCP + wDA) T - 10 (2.5 + wCP + wDA) T - 10 (2 + wCP + wDA) T - 28 ns ns ns ns Remarks 1. T = tCYK 2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. i: Number of idle states inserted when a write cycle follows the read cycle. 46 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (b) Read timing (high-speed DRAM access: on-page) (2/2) TCPW CLKOUT (Output) TO1 TDAW TO2 <58> <59> A0 to A23 (Output) Column address <63> <64> RASn (Output) <83> <81> <65> <82> UCAS (Output) LCAS (Output) <69> <68> WE (Output) <75> <72> <26> <79> <37> <70> OE (Output) <74> <80> D0 to D15 (I/O) <78> <27> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 47 PD70F3102-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time Symbol <24> <25> <56> <57> <58> <59> <60> tSWK tHKW tASR tRAH tASC tCAH tRC Conditions MIN. 15 2 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + w) T - 10 (3 + wRP + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (2.5 + wRH + wDA + w) T - 10 (1.5 + wDA + w) T - 10 (2 + wDA + w) T - 10 MAX. Unit ns ns ns ns ns ns ns RAS precharge time RAS pulse time <61> <62> tRP tRAS ns ns RAS hold time Column address read time (from RAS) CAS pulse width CAS to RAS precharge time CAS hold time CAS precharge time RAS column address delay time RAS to CAS delay time WE setup time (to CAS) WE hold time (from CAS) Data setup time (to CAS) Data hold time (from CAS) <63> <64> tRSH tRAL ns ns <65> <66> <67> <71> <76> <77> <84> <85> <86> <87> tCAS tCRP tCSH tCPN tRAD tRCD tWCS tWCH tDS tDH (1 + wDA + w) T - 10 (1 + wRH) T - 10 (2 + wRH + wDA + w) T - 10 (2 + wRP + wRH) T - 10 (0.5+ wRH) T - 10 (1 + wRH) T - 10 (1 + wRP + wRH) T - 10 (1 + wDA + w) T - 10 (1.5 + wRP + wRH) T - 10 (1.5 + wDA + w) T - 10 ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 48 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2) TRPW CLKOUT (Output) <58> <56> <57> <59> T1 TRHW T2 TDAW TW T3 A0 to A23 (Output) Row address Column address <63> <64> <62> <76> <61> RASn (Output) <60> <77> <66> UCAS (Output) LCAS (Output) <71> <67> <65> OE (Output) <84> <85> WE (Output) <86> <87> D0 to D15 (I/O) <24> <25> <24> <25> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 49 PD70F3102-33 (d) Write timing (high-speed page DRAM access: on-page) (1/2) Parameter Column address setup time Column address hold time RAS hold time Column address read time (from RAS) CAS pulse width CAS precharge time RAS hold time for CAS precharge WE setup time (to CAS) WE hold time (from CAS) Data setup time (to CAS) Data hold time (from CAS) WE read time (from RAS) WE read time (from CAS) Data setup time (to WE) Data hold time (from WE) WE pulse width Symbol <58> <59> <63> <64> tASC tCAH tRSH tRAL Conditions MIN. (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 MAX. Unit ns ns ns ns <65> <81> <83> <84> <85> <86> <87> <88> <89> <90> <91> <92> tCAS tCP tRHCP tWCS tWCH tDS tDH tRWL tCWL tDSWE tDHWE tWP wCP = 0 wCP = 0 wCP = 0 wCP = 0 wCP = 0 wCP 1 (1 + wDA) T - 10 (1 + wCP) T - 10 (2.5 + wCP + wDA) T - 10 wCPT - 10 (1 + wDA) T - 10 (0.5 + wCP) T - 10 (1.5 + wDA) T - 10 (1.5 + wDA) T - 10 (1 + wDA) T - 10 0.5T - 10 (1.5 + wDA) T - 10 (1 + wDA) T - 10 ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 50 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (d) Write timing (high-speed page DRAM access: on-page) (2/2) TCPW CLKOUT (Output) TO1 TDAW TO2 <58> <59> A0 to A23 (Output) Column address <63> <64> RASn (Output) <83> <81> UCAS (Output) LCAS (Output) <89> <88> <65> OE (Output) <84> <92> <85> WE (Output) <91> <90> <86> D0 to D15 (I/O) <87> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 51 PD70F3102-33 (e) Read timing (EDO DRAM) (1/3) Parameter Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from OE to data output Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time Column address read time (to RAS) CAS to RAS precharge time CAS hold time WE setup time (to CAS) WE hold time (from RAS) WE hold time (from CAS) RAS access time Access time from column address CAS access time Delay time from RAS to column address RAS to CAS delay time Output buffer turn-off delay time (from OE) Access time from CAS precharge CAS precharge time RAS hold time for CAS precharge Read cycle time RAS pulse width CAS pulse width Hold time from OE to CAS Off-page On-page Symbol <26> tSKID Conditions MIN. 18 MAX. Unit ns <27> tHKID 2 ns <37> <56> <57> <58> <59> <61> <64> <66> <67> <68> <69> <70> <73> <74> <75> <76> tDRDOD tASR tRAH tASC tCAH tRP tRAL tCRP tCSH tRCS tRRH tRCH tRAC tAA tCAC tRAD (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (0.5 + wDA) T - 10 (0.5 + wRP) T - 10 (2 + wCP + wDA) T - 10 (1 + wRP) T - 10 (1.5 + wRH + wDA) T - 10 (2 + wRP +wRH) T - 10 0.5T - 10 1.5T - 10 (2 + wRH + wDA) T - 28 (1.5 + wDA) T - 28 (1 + wDA) T - 28 (0.5 + wRH) T - 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns <77> <78> tRCD tOEZ (1 + wRH) T - 10 0 ns ns <80> <81> <83> <93> <94> <95> <96> <97> <98> tACP tCP tRHCP tHPC tRASP tHCAS tOCH1 tOCH2 tDHC (0.5 + wCP) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA + wCP) T - 10 (2.5 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 (2 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 0 (1.5 + wCP + wDA) T - 28 ns ns ns ns ns ns ns ns ns Data input hold time (from CAS) Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: Number of idle states inserted when a write cycle follows the read cycle. 52 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (e) Read timing (EDO DRAM) (2/3) Parameter Output enable access time Off-page Symbol <99> tOEA1 Conditions MIN. MAX. (2 + wRP + wRH + wDA) T - 28 (1 + wCP + wDA) T - 28 Unit ns On-page <100> tOEA2 ns Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) Preliminary Data Sheet U13844EJ2V0DS00 53 PD70F3102-33 (e) Read timing (EDO DRAM) (3/3) TRPW CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59> Column address Column address <64> <76> <61> RASn (Output) <67> <66> UCAS (Output) LCAS (Output) <68> <93> <80> WE (Output) <97> <96> Note OE (Output) <75> <74> D0 to D15 (I/O) <73> <99> BCYST (Output) <26> Data <98> <27> <27> <78> Data <100> <26> <37> <95> <69> <70> <77> <95> <81> <83> <75> <74> <94> T1 TRHW T2 TDAW TCPW TB TDAW TE Row address WAIT (Input) Note In case of on-page access from another cycle, while RASn is low level. Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 54 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 [MEMO] Preliminary Data Sheet U13844EJ2V0DS00 55 PD70F3102-33 (f) Write timing (EDO DRAM) (1/2) Parameter Row address setup time Row address hold time Column address setup time Column address hold time RAS precharge time RAS hold time Column address read time (to RAS) CAS to RAS precharge time CAS hold time Delay time from RAS to column address RAS to CAS delay time CAS precharge time RAS hold time for CAS precharge WE hold time (from CAS) Data hold time (from CAS) WE read time (to RAS) WE read time (to CAS) WE pulse width Write cycle time RAS pulse width CAS pulse width WE setup time (to CAS) Data setup time (to CAS) Off-page On-page Off-page On-page On-page Symbol <56> <57> <58> <59> <61> <63> <64> tASR tRAH tASC tCAH tRP tRSH tRAL Conditions MIN. (0.5 + wRP) T - 10 (0.5 + wRH) T -10 0.5T - 10 (0.5 + wDA) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA) T - 10 (2 + wCP + wDA) T - 10 MAX. Unit ns ns ns ns ns ns ns <66> <67> <76> tCRP tCSH tRAD (1 + wRP) T - 10 (1.5 + wRH + wDA) T - 10 (0.5 + wRH) T - 10 ns ns ns <77> <81> <83> <85> <87> <88> tRCD tCP tRHCP tWCH tDH tRWL wCP = 0 (1 + wRH) T - 10 (0.5 + wCP) T - 10 (2 + wCP + wDA) T - 10 (1 + wDA) T - 10 (0.5 + wDA) T - 10 (1.5 + twDA) T - 10 ns ns ns ns ns ns On-page <89> tCWL wCP = 0 (0.5 + wDA) T - 10 ns On-page <92> <93> <94> <95> <101> <102> <103> <104> tWP tHPC tRASP tHCAS tWCS1 tWCS2 tDS1 tDS2 wCP = 0 (1 + wDA) T - 10 (1 + wDA + wCP) T - 10 (2.5 + wRH + wDA) T - 10 (0.5 + wDA) T - 10 (1 + wRP + wRH) T - 10 ns ns ns ns ns ns ns ns wCP 1 wCPT - 10 (1.5 + wRP + wRH) T - 10 (0.5 + wCP) T - 10 Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 56 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (f) Write timing (EDO DRAM) (2/2) TRPW CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59> Column address <58> <59> Column address <64> <94> T1 TRHW T2 TDAW TCPW TB TDAW TE Row address <76> <61> RASn (Output) <67> <66> UCAS (Output) LCAS (Output) <93> <89> <88> RD (Output) OE (Output) <102> <101> <92> WE (Output) <85> <85> <95> <77> <95> <81> <83> <63> <103> <87> <104> <87> D0 to D15 (I/O) Data Data BCYST (Output) WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 57 PD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (1/3) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) Delay time from OE to data output Delay time from address to IOWR Address setup time (to IOWR) Delay time from IOWR to address Delay time from IOWR to RD Symbol <24> <25> <37> <41> <42> <43> <48> tSWK tHKW tDRDOD tDAWR tSAWR tDWRA tDWRRD wF = 0 wF = 1 IOWR low-level width Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time <50> <56> <57> <58> <59> <60> tWWRL tASR tRAH tASC tCAH tRC Conditions MIN. 15 2 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (2 + wRP + wRH + wDA + w) T -10 0.5T - 10 0 T - 10 (2 + wRH + wDA + w) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + wF + w) T - 10 (3 + wRP + wRH + wDA + wF + w) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA + wF + w) T - 10 (2 + wCP + wDA + wF + w) T - 10 (1 + wDA + wF + w) T - 10 (1 + wRP) T -10 (2 + wRH + wDA + wF + w) T - 10 (2 + wRP + wRH) T - 10 0.5T - 10 1.5T - 10 (2 + wRP + wRH) T - 10 (0.5 + wRH) T - 10 (1 + wRH) T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns RAS precharge time RAS hold time Column address read time for RAS CAS pulse width CAS to RAS precharge time CAS hold time WE setup time (to CAS) WE hold time (from RAS) WE hold time (from CAS) CAS precharge time RAS column address delay time RAS to CAS delay time <61> <63> <64> <65> <66> <67> <68> <69> <70> <71> <76> <77> tRP tRSH tRAL tCAS tCRP tCSH tRCS tRRH tRCH tCPN tRAD tRCD ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer 8. i: Number of idle states inserted when a write cycle follows the read cycle. 58 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (2/3) Parameter Output buffer turn-off delay time (from OE) Output buffer turn-off delay time (from CAS) CAS precharge time High-speed mode cycle time Symbol <78> tOEZ Conditions MIN. 0 MAX. Unit ns <79> tOFF 0 ns <81> <82> tCP tPC (0.5 + wCP) T - 10 (2 + wCP + wDA + wF + w) T - 10 (2.5 + wCP + wDA + wF + w) T - 10 (2.5 + wRH + wDA + wF + w) T - 10 (2.5 + wRP + wRH + wDA + wF + w) T - 10 (1.5 + wCP + wDA + wF + w) T - 10 (1.5 + wRH) T - 10 ns ns RAS hold time for CAS precharge <83> tRHCP ns RAS pulse width <94> tRASP ns Hold time from OE to CAS (from CAS) Off-page <96> tOCH1 ns On-page <97> tOCH2 ns Delay time from DMAAKm to CAS Delay time from IOWR to CAS <105> tDDACS ns <106> tDRDCS (1 + wRH) T - 10 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer 8. m = 0 to 3 Preliminary Data Sheet U13844EJ2V0DS00 59 PD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) external I/O transfer) (3/3) TRPW T1 TRHW T2 TDAW TW T3 TCPW TO1 TDAW TW TO2 CLKOUT (Output) <58> <56> <57> <59> A0 to A23 (Output) Row address <76> <61> Column address <94> <60> Column address <64> RASn (Output) <77> <66> <67> <65> <81> <83> <63> <69> UCAS (Output) LCAS (Output) <71> <96> <82> <70> <79> RD (Output) OE (Output) <105> <48> <97> DMAAKm (Output) <68> WE (Output) IORD (Output) <41> <106> <42> <50> <43> <78> <37> IOWR (Output) <24> D0 to D15 (I/O) <25> <24> Data <24> <25> <25> Data WAIT (Input) BCYST (Output) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits inserted to source-side access during DMA flyby transfer: 0 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 60 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (1/3) Parameter WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) IORD low-level width IORD high-level width Delay time from address to IORD Delay time from IORD to address Row address setup time Row address hold time Column address setup time Column address hold time Read/write cycle time RAS precharge time RAS hold time Column address read time for RAS CAS pulse width CAS to RAS precharge time CAS hold time CAS precharge time RAS column address delay time RAS to CAS delay time CAS precharge time High-speed page mode cycle time RAS hold time for CAS precharge WE hold time (from CAS) WE read time (to RAS) WE read time (to CAS) WE pulse width RAS pulse width Symbol <24> <25> <32> <33> <34> <35> <56> <57> <58> <59> <60> <61> <63> <64> <65> <66> <67> <71> <76> <77> <81> <82> <83> <85> <88> <89> <92> <94> tSWK tHKW tWRDL tWRDH tDARD tDRDA tASR tRAH tASC tCAH tRC tRP tRSH tRAL tCAS tCRP tCSH tCPN tRAD tRCD tCP tPC tRHCP tWCH tRWL tCWL tWP tRASP wCP = 0 wCP = 0 wCP = 0 Conditions MIN. 15 2 (2 + wRH + wDA + wF + w) T - 10 T - 10 0.5T - 10 (0.5 + i) T - 10 (0.5 + wRP) T - 10 (0.5 + wRH) T - 10 0.5T - 10 (1.5 + wDA + wF) T - 10 (3 + wRP + wRH + wDA + wF + w) T - 10 (0.5 + wRP) T - 10 (1.5 + wDA + wF) T - 10 (2 + wCP + wDA + wF + w) T - 10 (1 + wDA + wF) T - 10 (1 + wRP) T - 10 (2 + wRH + wDA + wF + w) T - 10 (2 + wRP + wRH + w) T - 10 (0.5 + wRH) T - 10 (1 + wRH + w) T - 10 (0.5 + wCP + w) T - 10 (2 + wCP + wDA + wF + w) T - 10 (2.5 + wCP + wDA + w) T - 10 (1 + wDA ) T - 10 (1.5 + wDA + w) T - 10 (1 + wDA + w) T - 10 (1 + wDA + w) T - 10 (2.5 + wRH + wDA + wF + w) T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer. 8. i: Number of idle states inserted when a write cycle follows the read cycle. 9. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 61 PD70F3102-33 (h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (2/3) Parameter WE setup time (to CAS) Off-page On-page Symbol <101> <102> <105> tWCS1 tWCS2 tDDACS Conditions wCP = 0 wCP 1 MIN. (1 + wRH + wRP + w) T - 10 wCPT - 10 (1.5 + wRH + w) T - 10 MAX. Unit ns ns ns Delay time from DMAAKm to CAS Delay time from IORD to CAS Delay time from WE to IORD <106> <107> tDRDCS tDWERD wF = 0 wF = 1 (1 + wRH + w) T - 10 0 T - 10 ns ns ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wF: Number of waits inserted to source-side access during DMA flyby transfer 7. m = 0 to 3 62 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (h) DMA flyby transfer timing (external I/O DRAM (EDO, high-speed page) transfer) (3/3) TRPW T1 TRHW TW T2 TDAW T3 TCPW TW TO1 TDAW TO2 CLKOUT (Output) <56> <57> <58> <59> A0 to A23 (Output) Row address <76> <61> Column address <94> <60> Column address <64> RASn (Output) <77> <66> <67> <65> <81> <63> UCAS (Output) LCAS (Output) <71> <82> <83> RD (Output) OE (Output) <101> <85> <102> <88> <89> WE (Output) <105> <92> DMAAKm (Output) IOWR (Output) <106> <34> <107> <35> IORD (Output) <32> <25> <33> Data <24> <24> <25> <24> <25> Data D0 to D15 (I/O) WAIT (Input) BCYST (Output) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits inserted to source-side access during DMA flyby transfer: 0 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Preliminary Data Sheet U13844EJ2V0DS00 63 PD70F3102-33 (i) CBR refresh timing Parameter RAS precharge time RAS pulse width CAS hold time REFRQ pulse width Symbol <61> <62> <108> <109> tRP tRAS tCHR tWRFL Conditions MIN. (1.5 + wRRW) T - 10 (1.5 + wRCW (1.5 + wRCW Note MAX. Unit ns ns ns ns ) T - 10 ) T - 10 Note Note (3 +wRRW + wRCW T - 10 ) RAS precharge CAS hold time REFRQ active delay time (from CLKOUT) REFRQ inactive delay time (from CLKOUT) CAS setup time <110> <111> tRPC tDKRF (0.5 + wRRW) T - 10 2 10 ns ns <112> tHKRF 2 10 ns <113> tCSR T - 10 ns Note wRCW is inserted for at least 1 clock, regardless of the setting of bits RCW0 to RCW2 of register RWC. Remarks 1. T = tCYK 2. wRRW: Number of waits specified by bits RRW0 and RRW1 of register RWC 3. wRCW: Number of waits specified by bits RCW0 to RCW2 of register RWC. TRRW CLKOUT (Output) <111> <109> REFRQ (Output) <112> T1 T2 TRCWNote TRCW T3 TI <61> <62> RASn (Output) <110> <110> UCAS (Output) LCAS (Output) <113> <108> Note This TRCW is always inserted, regardless of the setting of bits RCW0 to RCW2 of register RWC. Remarks 1. These timings are for the following cases: Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1 Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 2 2. n = 0 to 7 64 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (j) CBR self refresh timing Parameter REFRQ active delay time (from CLKOUT) REFRQ inactive delay time (from CLKOUT) CAS hold time RAS precharge time Symbol <111> tDKRF Conditions MIN. 2 MAX. 10 Unit ns <112> tHKRF 2 10 ns <114> <115> tCHS tRPS -5 (1 + 2wSRW) T - 10 ns ns Remarks 1. T = tCYK 2. wSRW: Number of waits specified by bits SRW0 to SRW2 of register RWC. TRRW CLKOUT (Output) TH TH TH TRCW TH TI TSRW TSRW <111> <112> REFRQ (Output) <115> RASn (Output) <114> UCAS (Output) LCAS (Output) Output signals other than above Remarks 1. These timings are for the following cases: Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1 Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 1 Number of waits (TSRW) specified by bits SRW0 to SRW2 of register RWC: 2 2. Broken lines indicate high impedance. 3. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 65 PD70F3102-33 (7) DMAC timing Parameter DMARQn setup time (to CLKOUT) DMARQn hold time (from CLKOUT) DMAAKn output delay time (from CLKOUT) DMAAKn output hold time (from CLKOUT) TCn output delay time (from CLKOUT) TCn output hold time (from CLKOUT) Symbol <116> tSDRK Conditions MIN. 15 MAX. Unit ns <117> <118> <119> tHKDR1 tHKDR2 tDKDA 2 Until DMAAKn 2 10 ns ns ns <120> tHKDA 2 10 ns <121> tDKTC 2 10 ns <122> tHKTC 2 10 ns Remark n = 0 to 3 CLKOUT (Output) <117> <116> DMARQn (Input) <116> <119> DMAAKn (Output) <120> <118> <122> <121> TCn (Output) Remark n = 0 to 3 66 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 [MEMO] Preliminary Data Sheet U13844EJ2V0DS00 67 PD70F3102-33 (8) Bus hold timing (1/2) Parameter HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to HLDAK HLDRQ high-level width HLDAK low-level width Delay time from CLKOUT to bus float Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK Symbol <123> <124> tSHRK tHKHR Conditions MIN. 15 2 MAX. Unit ns ns <125> tDKHA 2 10 ns <126> <127> <128> tWHQH tWHAL tDKCF T + 17 T-8 10 ns ns ns <129> tDHAC 0 ns <130> tDHQHA1 2.5T ns <131> tDHQHA2 0.5T 1.5T ns Remark T = tCYK 68 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (8) Bus hold timing (2/2) T1 CLKOUT (Output) <123> <123> <124> <123> <124> <123> <126> T2 T3 TI TH TH TH TI T1 HLDRQ (Intput) <125> <130> <125> <131> HLDAK (Output) <127> <128> <129> A0 to A23 (Output) Address Undefined D0 to D15 (I/O) Data CSn/RASn (Output) BCYST (Output) RD (Output) WE (Output) UCAS (Output) LCAS (Output) Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 7 Preliminary Data Sheet U13844EJ2V0DS00 69 PD70F3102-33 (9) Interrupt timing Parameter NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width Symbol <132> <133> <134> <135> tWNIH tWNIL tWITH tWITL Conditions MIN. 500 500 4T + 10 4T + 10 MAX. Unit ns ns ns ns Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153 2. T = tCYK <132> <133> NMI (Input) <134> <135> INTPn (Input) Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153 (10) RPU timing Parameter TI1n high-level width TI1n low-level width TCLR1n high-level width TCLR1n low-level width Symbol <136> <137> <138> <139> tWTIH tWTIL tWTCH tWTCL Conditions MIN. 3T + 18 3T + 18 3T + 18 3T + 18 MAX. Unit ns ns ns ns Remarks 1. n = 0 to 5 2. T = tCYK <136> <137> TI1n (Input) <138> <139> TCLR1n (Input) Remark n = 0 to 5 70 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 (11) UART0, UART1 timing (synchronized with clock, master mode only) Parameter SCKn cycle SCKn high-level width SCKn low-level width RXDn setup time (to SCKn) RXDn hold time (from SCKn) TXDn output delay time (from SCKn) TXDn output hold time (from SCKn) Symbol <140> <141> <142> <143> <144> <145> tCYSK0 tWSK0H tWSK0L tSRXSK tHSKRX tDSKTX Conditions Output Output Output MIN. 250 0.5tCYSK0 - 20 0.5tCYSK0 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns <146> tHSKTX 0.5tCYSK0 - 5 ns Remark n = 0, 1 <140> <142> <141> SCKn (I/O) <143> <144> RXDn (Input) Input data <145> <146> TXDn (Output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 Preliminary Data Sheet U13844EJ2V0DS00 71 PD70F3102-33 (12) CSI0 to CSI3 timing (a) Master mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO 0.5tCYSK1 - 5 Conditions Output Output Output MIN. 100 0.5tCYSK1 - 20 0.5tCYSK1 - 20 30 0 20 MAX. Unit ns ns ns ns ns ns ns Remark n = 0 to 3 (b) Slave mode Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) Symbol <147> <148> <149> <150> <151> <152> <153> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO tWSK1H Conditions Input Input Input MIN. 100 30 30 10 10 30 MAX. Unit ns ns ns ns ns ns ns Remark n = 0 to 3 <147> <149> <148> SCKn (I/O) <150> <151> Sln (Input) Input data <152> <153> SOn (Output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 3 72 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 A/D Converter Characteristics (TA = -40 to +85C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V, HVDD - 0.5 V AVDD HVDD, Output Pin Load Capacitance: CL = 50 pF) Parameter Resolution Overall error Quantization error Conversion time Sampling time Zero scale error Scale error Linearity error Analog input voltage Analog input resistance AVREF input voltage AVREF input current AVDD current Symbol - - - tCONV tSAMP - - - VIAN RAN AVREF AIREF AIDD AVREF = AVDD 4.5 -0.3 2 5.5 1.6 6 5 833 2 2 1 AVREF + 0.3 Conditions MIN. 10 4 1/2 10 TYP. MAX. Unit bit LSB LSB s ns LSB LSB LSB V M V mA mA Preliminary Data Sheet U13844EJ2V0DS00 73 PD70F3102-33 4.2 Flash Memory Programming Mode Basic Characteristics (TA = 10 to 40C (When Rewriting), TA = -40 to +85C (Other Than When Rewriting)) Parameter Operating frequency Power supply voltage Symbol fX VDD HVDD VPP VPPH VDD high-level detection VPP high-voltage detection 0.8VDD 7.5 VDD 7.8 Conditions MIN. 20 TYP. MAX. 33 3.6 5.5 1.2VDD 8.1 Unit MHz V V V V HVDD supply current VPP supply current Number of writes IDD IPP CWRT VPP = 8.1 V K category P category Note 50 150 5 10 20 mA mA Times Times Times Note Other than K, P Note category Write time Erase time tWRT tERASE Per 1 byte K, P category Note 20 200 60 s s (Recommendation: Step erase = 5 s) Other than K, P Note category (Recommendation: Step erase = 0.2 s) Temperature during write TPRG K, P category Note 20 s 10 10 40 85 C C Other than K, P Note category Note The category is indicated by the fifth letter from the left of the lot number. Caution The I category is applied to engineering samples only. The number of rewrites is not guaranteed for the I category products. 74 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 Serial Write Operation Characteristics Parameter VDD to VPP set time VPP to RESET set time RESET to VPP count start time Count execution time VPP counter high-level width VPP counter low-level width VPP counter rise time VPP counter fall time Symbol <201> <202> <203> <204> <205> <206> <207> <208> tDRPSR tPSRRF tRFOF tCOUNT tCH tCL tR tF 1 1 3 3 VPP = 7.8 V Conditions MIN. 200 1 5T + 500 10 TYP. MAX. Unit ns s s ms s s s s VDD, HVDD VDD, HVDD 0V <201> VPPH VPP HVDD <208> 0V <202> HVDD RESET (Input) 0V <203> <206> <205> <204> <207> Preliminary Data Sheet U13844EJ2V0DS00 75 PD70F3102-33 5. PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I M J K S P N S L M NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. S144GJ-50-8EU-3 76 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I M J P K S L M N NOTE S Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.4 0.100.05 3 +4 -3 1.50.1 S144GJ-50-UEN Preliminary Data Sheet U13844EJ2V0DS00 77 PD70F3102-33 6. RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document "Semiconductor Device Mounting Technology Manual (C10535E)". For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions PD70F3102GJ-33-8EU: 144-pin plastic LQFP (Fine Pitch) (20 x 20) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at Note 210C or higher), Count: Twice or less, Exposure limit: 3 days (after that, prebake at 125C for 10 hours) Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) - Recommended Condition Symbol IR35-103-2 Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution The recommended soldering conditions of the PD70F3102GJ-33-UEN are yet to be determined. 78 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 [MEMO] Preliminary Data Sheet U13844EJ2V0DS00 79 PD70F3102-33 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 80 Preliminary Data Sheet U13844EJ2V0DS00 PD70F3102-33 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Preliminary Data Sheet U13844EJ2V0DS00 81 PD70F3102-33 Related Documents PD70F3102A-33 Data Sheet (U13845E) PD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet (U13995E) PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E) Reference Materials Electrical Characteristics for Microcomputer (IEI-601) Note This document number is that of Japanese version. The related documents in this publication may include preliminary versions. However, preliminary versions are not marked as such. The V850E/MS1 is a trademark of NEC Corporation. * The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M5 98. 8 Note |
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